The present invention generally relates to semiconductor device and more particularly to a semiconductor device and fabrication process thereof in which the operational speed there is improved by application of stress.
With the progress in the art of device miniaturization, ultrafine and ultra high-speed semiconductor devices having the gate length of 100 nm or less are becoming possible.
With such ultrafine and ultrahigh speed transistors, the area of the channel region right underneath the gate electrode is reduced significantly as compared with conventional semiconductor devices, and thus, the mobility of electrons or holes traveling through the channel region is influenced heavily by the stress applied to such a channel region. Thus, various attempts have been made for optimizing the stress applied to such a channel region, in the prospect of improving the operational speed of the semiconductor device further.
Generally, with semiconductor devices that use a silicon substrate for the channel, the mobility of holes is much smaller than the mobility of electrons, and thus, it is an important point for designing a semiconductor integrated circuit to improve the operational speed of the p-channel MOS transistor that uses holes as the carriers.
With such a p-channel MOS transistor, it is known that the mobility of the carriers is improved by applying a uniaxial compressive stress to the channel region, and thus, there is proposed a construction shown schematically in FIG. 1 as the means for applying the compressive stress to the channel region.
Referring to FIG. 1, a gate electrode 3 is formed on a silicon substrate 1 in correspondence to a channel region via a gate insulation film 2, and p-type diffusion regions 1a and 1b are formed in the silicon substrate 1 at both lateral sides of the gate electrode 3 so as to define the channel region therebetween. Further, sidewall insulation films 3A and 3B are formed on the side wall surface of the gate electrode 3 such that the sidewall insulation films 3A and 3B cover a part of the surface of the silicon substrate 1.
It should be noted that the diffusion regions 1a and 1b function respectively as the source and drain extension regions of the MOS transistor, and the flow of the holes transported through the channel region from the diffusion region 1a to the diffusion region 1b right underneath the gate electrode 3 is controlled by a gate voltage applied to the gate electrode 3.
In the construction of FIG. 1, SiGe mixed crystal layers 1A and 1B are formed in the silicon substrate 1 at respective outer sides of the sidewall insulation films 3A and 3B with epitaxial relationship to the silicon substrate 1, and source and drain regions of p-type are formed respectively in the SiGe mixed crystal layers 1A and 1B in continuation to the diffusion regions 1a and 1b. 
In the MOS transistor of the construction of FIG. 1, it should be noted that the SiGe mixed crystal layers 1A and 1B have a larger lattice constant as compared with the lattice constant of the silicon substrate 1, and thus, there is formed a compressive stress in the SiGe mixed crystal layers 1A and 1B as shown by an arrow a. As a result, the SiGe mixed crystal layers 1A and 1B undergo straining in a direction generally perpendicular to the surface of the silicon substrate 1 as shown with an arrow b.
Because the SiGe mixed crystal layers 1A and 1B are formed in epitaxial relationship to the silicon substrate 1, such a strain in the SiGe mixed crystal layers 1A and 1B shown by the arrow b induces a corresponding strain in the channel region of the silicon substrate as represented with the arrow c, and as a result of such a strain, there is induced a uniaxial compressive stress in the channel region as shown in arrow d.
With the MOS transistor of FIG. 1, the symmetry of the Si crystal that constitutes the channel region is modulated locally as a result of such a uniaxial compressive stress applied to the channel region, while such a change of symmetry resolves the degeneration of valence band for the heavy holes and light holes, and there is caused increase of hole mobility in the channel region. With this, the operational speed of the transistor is improved. Such increase of hole mobility caused by the stress induced locally in a channel region and associated improvement of the transistor operational speed appear especially conspicuously in the ultrafine semiconductor devices having a gate length of 100 nm or less.